Marvel的早期芯片制作赌博在人工智能需求下得到回报
八年前，芯片制造商马维尔科技股份有限公司决定用纳米计来进行跳跃，其轨迹自此稳步上扬。
在半导体制造中，纳米计指定识别出几代芯片制造技术，称为过程节点，而不是晶体管的精确物理维度。 先进的过程节点一般可以使晶体管密度更大，提高性能和功率效率。
芯片制造者通常遵循纳米尺寸下移的一套程序，跳出一个级别构成重大风险。 马维尔决定下注
“2018年前后，2019年，我们做出了一个决定，如果我们想做数据基础设施，我们需要成为领导者，“所以，我们跳过了7纳米。 我们的产品像12和16纳米下一个逻辑是7。 我们一直跳到5... 我们一直走 3纳米，2纳米，14安格斯特龙。 我们一直在运行这个游戏本，它确实成为我们成长在云中的领导者的基础。
Chu在CUBE,SiliconANGLE Media的直播室独家播出时，与CUBE的John Furrier为CUBE + NYSE Wired:AI Factories – 未来访谈系列的数据中心交谈。 他由位于马维尔的数据中心联网商业集团执行副总裁和总经理大卫·拉佐夫斯基(英语：David Lazovsky (right))加入，他们讨论了公司如何围绕提高企业AI架构的效率来构建业务。 (* 以下披露。 )
AI 架构的光学解决方案
Marvel平台的基石是串行器/deserializer(SerDes)技术，它为AI集群、云数据中心和企业网络提供高速、多基加比特数据传输。 扩大AI基础设施是当今数据中心面临的一个关键挑战，而Marvel一直在使用SerDes来提高电力效率。
9月，发布 2-南克仪光学互联技术公司设计支持AI扩能架构，将多计算机和内存资源紧密相接，作为更大的系统运行。
拉佐夫斯基告诉CUBE, “为什么从铜到光学的扩大的互联性如此重要，因为处理器到处理器的数据传输，大约占数据传输总量的85%, “如果你能对能源效率产生积极影响，就可以显著地移动针头。 利用光学和SerDes技术
马维尔对高效建筑的关注也导致了高带宽记忆的进步。 8月，宣布公司设计了一个光子相机Fabric记忆模块，目的是在整个AI基础设施中建立共享相机层。 该技术结合了DDR5内存，高带宽内存缓存和光学连通性，使得内存资源可以跨AI系统共享。
“Marvel首次发展出光学相通的高容量、高带宽内存，” “有两堆高带宽内存，这支持一个模块，最多可有八堆双相数据率5。 它为您提供了首次从计算中解析内存容量的能力。”
Marvell在记忆和光学联网方面的进步加强了其在AI基础设施市场中的地位。 Nvidia Corp. 宣布是今年早些时候对该公司的20亿美元投资，而Marverl最近宣布公司同意为Google有限责任公司设计定制AI芯片。
“这是CapEx在人类历史上最大的建设，”Chu 称。 “在我们的连通业务、我们的网络业务和我们的定制业务方面，我们紧贴着这些市场中增长最快的部分。 我们有领先的技术，有顾客的信誉，有执行的记录。”
以下是完整的视频采访，SiliconANGLE的部分内容和CUBE对CUBE + NYSE Wired: AI Factories – 未来访谈系列的数据中心的报导：
(*披露：CUBE是CUBE + NYSE Wired:AI Factories – 未来访谈系列的数据中心的付费媒体合作伙伴。 无论是CUBE事件报道的发起人Marvell还是其他发起人，都没有对CUBE或SiliconANGLE上的内容进行编辑控制。.
照片：SiliconANGLE
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Marvell’s early chipmaking gamble pays off amid AI demand
Eight years ago, chipmaker Marvell Technology Inc. decided to play leapfrog with nanometers, and its trajectory has been steadily upward since.
In semiconductor manufacturing, nanometer designations identify generations of chipmaking technology, known as process nodes, rather than the exact physical dimensions of transistors. Advanced process nodes generally enable greater transistor density and improvements in performance and power efficiency.
Chipmakers have usually followed a set progression downward in nanometer sizes, and skipping a level constituted a significant risk. Marvell decided to make that bet.
“Back around 2018, 2019 ,we made a decision that if we wanted to do data infrastructure, we needed to be a leader and not a follower, and that meant jumping to the latest process node with the best technology,” said Will Chu (pictured, left), executive vice president and general manager of the Custom Cloud Solutions Business Unit, at Marvell. “So, we skipped 7 nanometer. We had products like 12 and 16 nanometer and the next logical one would have been 7. We jumped all the way to 5…we kept going – 3 nanometer, 2 nanometer, 14 angstrom. We’ve been running that playbook, and it’s really served as the foundation for our growth to be a leader in the cloud.”
Chu spoke with theCUBE’s John Furrier for theCUBE + NYSE Wired: AI Factories – Data Centers of the Future interview series, during an exclusive broadcast on theCUBE, SiliconANGLE Media’s livestreaming studio. He was joined by David Lazovsky (right), executive vice president and general manager of the Data Center Networking Business Group at Marvell, and they discussed how the company has built its business around improving efficiency for enterprise AI architectures. (* Disclosure below.)
Optical solutions for AI architectures
A cornerstone of Marvell’s platform is serializer/deserializer (SerDes) technology, which provides high-speed, multi-gigabit data transmission for AI clusters, cloud data centers, and enterprise networking. Scaling AI infrastructure is a critical challenge in today’s data centers, and Marvell has been using SerDes to improve power efficiency.
In September, the company unveiled 2-nanometer optical interconnect technologies designed to support AI scale-up architectures, which tightly connect multiple computing and memory resources to operate as a larger system.
“Why interconnectivity with scale-up moving from copper to optics is so important is because processor-to-processor data transmission, roughly 85% of total data transmission, is happening inside of these scale-up networks, and only 15% across the scale-out network,” Lazovsky told theCUBE. “If you can positively impact the energy efficiency, you can move the needle significantly. We’re developing technologies that leverage optics and SerDes … that significantly reduce the total power consumption.”
Marvell’s focus on efficient architecture has also led to advances in high-bandwidth memory. In August, the company announced a Photonic Fabric Memory Module designed to enable a shared-memory tier across AI infrastructure. The technology combines DDR5 memory, high-bandwidth memory caching and optical connectivity to allow memory resources to be shared across AI systems.
“For the first time ever, Marvell has developed optically interconnected high capacity, high bandwidth memory,” Lazovsky said. “There are two stacks of high bandwidth memory, and this supports a module with up to eight stacks of Double Data Rate 5. It provides you the ability to decouple memory capacity from compute for the first time.”
Marvell’s advances in memory and optical networking have strengthened its position in the AI infrastructure market. Nvidia Corp. announced a $2 billion investment in the firm earlier this year, and Marvell recently announced an agreement that it would design custom AI chips for Google LLC.
“This is the biggest buildout in CapEx in human history,” Chu said. “In terms of our connectivity business, our networking business, and our custom business, we’re attached to the fastest growing part of those markets. We have the leading technology, we have the customer credibility, a track record of execution.”
Here’s the complete video interview, part of SiliconANGLE’s and theCUBE’s coverage of theCUBE + NYSE Wired: AI Factories – Data Centers of the Future interview series:
(* Disclosure: TheCUBE is a paid media partner for theCUBE + NYSE Wired: AI Factories – Data Centers of the Future interview series. Neither Marvell, the sponsor of theCUBE’s event coverage, nor other sponsors have editorial control over content on theCUBE or SiliconANGLE.)
Photo: SiliconANGLE
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