文 | 半导体产业纵横
伴随AI芯片的不断发展，先进封装已经成为老生常谈的概念。TrendForce近日发布报告，对AI芯片先进封装竞争格局给出判断。报告指出，尽管英特尔EMIB-T等方案正在争取AI芯片客户，但台积电CoWoS-L凭借技术成熟度和良率优势，预计到2028年仍将是AI芯片主流先进封装方案。这一判断意味着，未来几年AI芯片的封装路线竞争将围绕CoWoS-L展开，其他方案想要切入这一市场，还需要在成熟度和良率上拿出更有说服力的表现。
AI芯片的封装为什么越来越“大”？
AI芯片正在变得越来越大。但这里的大，首先指向封装，而不是单颗计算芯片本身。随着大模型参数规模和推理任务复杂度持续提升，AI加速器需要更高算力和更大内存带宽。单颗芯片很难独立承担所有需求，Chiplet和HBM因此成为提升系统性能的重要手段。芯片内部需要连接的计算资源和存储资源越来越多，压力直接传导到封装环节。
英伟达Rubin平台是一个很好的例子。据公开信息，Rubin GPU采用3360亿晶体管，配备HBM4，单颗GPU最高可提供288GB显存和22TB/s内存带宽。AMD同样在加速迭代，Instinct MI400系列采用Chiplet架构，下一代MI455X由8个计算芯片组成，面向72颗GPU组成的Helios机架级系统。这些产品的一个共同点，就是单个封装内集成的计算芯片和HBM数量在增加。从封装尺寸来看，英伟达Blackwell GPU已经达到约3.3倍掩模极限，下一代Rubin平台预计将达到4倍。
当计算芯片和HBM数量不断增加，传统单颗芯片加外部存储的方式越来越难以满足AI系统对带宽和数据传输效率的要求。把更多计算芯片和HBM放进同一个先进封装，可以缩短芯片之间的数据传输距离，并通过高密度互连提供更大带宽。因此，AI芯片的大最终反映为封装尺寸的扩大。真正持续增大的，是一个先进封装内部需要集成的计算芯片、Chiplet、HBM和高速互连的总规模，而不是单颗逻辑Die的横向面积。
从数据上看，封装尺寸的扩大已经持续了将近十年。据IDTechEx发布的先进封装技术趋势报告，台积电CoWoS硅中介层尺寸从2016年的约1.5倍掩模尺寸，约1287mm2，演进到当前的3.3倍，约2831mm2，并计划在2026年扩展至5.5倍，约4719mm2。封装尺寸的扩大也直接反映在设备端，HANMI Semiconductor新推出的FC Bonder 75支持的封装尺寸为75mm x 75mm，而传统通用封装尺寸仅为20mm x 20mm。
推动封装变大的力量还在从GPU扩展到AI ASIC。TrendForce数据显示，NVIDIA高端GPU 2026年出货预计年增约30%，AMD于2026下半年力推MI400和MI450。CSP自研ASIC方面，2026年出货量与动能以Google最为强劲，TPU v7为主力。AWS从下半年开始逐步推进Trainium v3，Microsoft和Meta目前仍以GPU Server为主，ASIC规划量能较小。不同类型的AI芯片都在向更高集成度发展，意味着封装需要承载的计算和存储资源持续增加。
封装尺寸为什么遇到瓶颈？
封装尺寸不断扩大之后，问题随之而来。这么大的中介层还能否制造出来？
传统2D封装中，芯片通过键合线连接到封装基板，基板内部的金属布线和过孔负责信号传输。这条路径很长，引入的电阻和电感较大，信号延迟和功耗都成为瓶颈。当多个芯片分开封装并放置在PCB上时，信号在它们之间传输的物理距离相当长，为了驱动信号跨越这段距离，功耗会显著增加，芯片之间的整体通信带宽也因此受到限制。
面积则是另一个问题。在PCB上放置多个大型封装会占用庞大的物理面积，对于空间受限的产品来说难以接受。更关键的是，PCB的布线宽度与芯片的凸点和微凸点之间存在巨大差距，这种差距限制了I/O的数量和密度，使得传统封装方式很难满足AI和高性能计算对高带宽、低延迟和小型化的要求。互连长度、物理面积和I/O密度三个方向同时受限，2D封装已经很难继续承载AI芯片的集成需求。
为了解决这些问题，一些厂商提出了2.5D封装方案。其核心思路是引入一层中介层，将多个芯片并排放置在中介层上，而不是直接放在PCB上。芯片通过微凸点连接到中介层，中介层内部包含极其精细的重分布层，负责芯片之间高密度、短距离的水平通信。中介层再通过硅通孔垂直连接到下方的封装基板。这样一来，芯片之间的互连距离被大幅缩短，信号完整性和带宽得到改善，同时绕开了单颗芯片无法突破的掩模极限，也为后续集成更多计算芯片和HBM提供了可行的路径。
也正是在2.5D封装这条路径上，台积电的CoWoS逐渐成为代表性方案。
CoWoS-L：2.5D主流方案
台积电的CoWoS是典型的2.5D封装方案，其核心就是在一个封装中整合多个SoC或Chiplet与HBM。
目前台积电的CoWoS家族主要包括三个成员，分别是CoWoS-S、CoWoS-R和CoWoS-L。三者最大的不同，在于中介层采用了不同的实现方式。CoWoS-S使用大面积硅中介层，在其上通过布线实现高密度互连，将逻辑芯片和HBM集成到一起。CoWoS-R则使用RDL（重布线层）取代硅中介层。RDL由聚合物和铜布线层构成，在保持较高互连性能的同时具备更好的机械柔性，可以较容易地扩展，以支持更大的封装尺寸。
CoWoS-L在前两者的基础上进行了融合，是一种更加灵活的方式。它基于RDL进行布线，同时嵌入被称为局部硅互连的小型硅片。CoWoS-L的L字母，对应的就是Local Silicon Interconnect（LSI），也就是局部硅互连。台积电表示，LSI通过多层亚微米级铜线路实现高布线密度的die-to-die互连，可以根据不同产品需求承担SoC-to-SoC、SoC-to-Chiplet以及SoC-to-HBM等连接。与此同时，RDL负责更大范围的信号和电源传输。这样一来，高密度互连集中在真正需要精细连接的区域，而不是让整块中介层都承担同样的高密度布线。
这种结构上的变化，是CoWoS-L能够继续扩大封装尺寸的关键。对于超大规模AI芯片来说，并不是封装里的每一个区域都需要同样高的布线密度。如果所有区域都采用硅中介层的高密度布线方式，随着面积扩大，制造成本和工艺复杂度也会同步增加。CoWoS-L通过LSI与RDL的组合，把高密度互连用在真正需要的位置，再利用RDL承担更大范围的连接和供电，因此可以在保持关键区域互连能力的同时，进一步扩展整个封装的尺寸。台积电目前已经将CoWoS-L定位为支持更大尺寸HPC产品的封装方案，并持续扩大其中介层尺寸，以集成更多硅芯片和HBM。
这种局部高密度加上大面积扩展的思路，也让CoWoS-L与AI芯片的Chiplet架构形成了较好的匹配。未来的AI加速器可能同时包含多个计算Die、不同功能的Chiplet以及多颗HBM，而不同芯片之间的数据流并不完全相同。有些链路需要极高的带宽和极短的连接距离，有些则更侧重区域间的信号与电源分配。CoWoS-L可以针对这些不同需求配置互连结构，也可以在SoC下方进一步整合独立的嵌入式深沟槽电容eDTC，用于改善电源管理。换句话说，封装开始从单纯的连接芯片，逐渐转向针对整个计算系统进行互连和供电设计。
从实际尺寸演进来看，CoWoS-L也已经走出了实验室。台积电首款3.5倍reticle尺寸的CoWoS-L已经于2024年进入量产。根据台积电2025年公开资料，公司完成了5.5倍mask/reticle尺寸CoWoS方案的认证，并计划于2026年启动量产，以满足AI和HPC对更高性能的需求。台积电还表示，将继续扩大CoWoS中介层尺寸，以容纳更多先进制程芯片和HBM。
这一技术路线也已经开始向产品端落地。TrendForce指出，NVIDIA和AMD的AI加速器已经采用CoWoS-L，Meta的MTIA 400也使用了这一封装方案。随着云服务商持续发展自研ASIC，需要在同一封装中集成更多SoC、Chiplet和HBM，微软和AWS预计也将在2027年导入CoWoS-L。TrendForce认为，CoWoS-L凭借技术成熟度和良率优势，预计到2028年仍将保持AI芯片主流先进封装方案。
不过，CoWoS-L也并非2.5D封装唯一的实现路径。
EMIB，另一条技术路线怎么走
如果说CoWoS-L是在中介层上做文章，那么英特尔的EMIB走的是另一条2.5D封装路线。EMIB全称Embedded Multi-die Interconnect Bridge，即嵌入式多芯粒互连桥。它没有采用覆盖整个封装区域的大面积硅中介层，而是把尺寸较小的硅桥嵌入封装基板中，只在需要进行高密度互连的芯片之间建立连接。芯片依然以并排的方式放置在基板上，但彼此之间可以通过硅桥完成高密度、高速的数据传输。
与大面积硅中介层相比，EMIB的思路更加局部化。硅桥只出现在芯片需要高速通信的区域，因此并不需要为整个封装铺设一层完整的硅中介层。英特尔介绍，EMIB可以针对不同的die-to-die连接定制桥的尺寸和类型，在逻辑芯片与逻辑芯片、逻辑芯片与HBM之间建立高密度互连，同时避免让所有信号和电源都经过一整块硅中介层。这样既可以提高不同芯片之间的互连密度，也能够在封装结构和成本之间进行权衡。
这种结构尤其适合Chiplet架构。一个封装中可以放入来自不同工艺节点、不同功能的多个芯粒，再通过不同位置的EMIB桥接起来，让CPU、GPU、I/O以及HBM等不同类型的芯片形成一个完整系统。英特尔已经将EMIB用于大规模量产，并表示其封装组装良率可以达到与复杂度相当的传统FCBGA封装接近的水平。
不过，EMIB也有自己的限制。由于硅桥嵌入的是封装基板，而不是覆盖整个封装的大面积硅中介层，芯片之间的高密度连接最终仍然受到基板布线能力的影响。随着HBM带宽不断提升，AI芯片内部的数据传输量越来越大，除了互连密度之外，供电也开始成为一个重要问题。对于高功耗AI芯片来说，如何在有限的封装空间里把足够大的电流快速、稳定地输送到芯片，同时降低电源噪声和传输损耗，已经成为EMIB进一步发展的关键。
EMIB-T就是在这一背景下出现的升级方案。其中的T对应Through-Silicon Via，也就是硅通孔。英特尔在EMIB原有的局部硅桥基础上加入TSV，使电源可以通过硅桥直接从封装基板垂直送往上方芯片，而不必再绕行其他布线层。这样做可以缩短供电路径，提高供电密度，并改善高功耗、高带宽应用中的电源完整性。英特尔公开资料显示，EMIB-T还可以在桥内整合多层铜电源、地线网络以及高密度电容，从而进一步降低供电网络阻抗和噪声。
如果把EMIB看成一座连接芯片的桥，那么EMIB-T最大的变化就是给这座桥增加了一条垂直通道。过去主要解决的是芯片之间怎么通信，加入TSV之后，封装还可以进一步解决电怎么直接送上去的问题。英特尔在2026年ECTC上展示的EMIB-T方案，已经将第一层互连凸点间距缩小至25微米，封装尺寸扩大到120mm×120mm，并支持超过9个reticle面积的计算与存储芯片集成，同时面向12 Gb/s HBM4e和64 Gb/s UCIe等高速互连。
这意味着EMIB正在从最初的局部硅桥进一步向更大尺寸、更高互连密度和更强供电能力发展。TrendForce指出，随着CoWoS-L封装成本和台积电先进封装产能持续受到关注，EMIB成为部分AI芯片厂商考虑的替代方案，Google预计将在2027年采用EMIB-T，AWS也正在测试EMIB技术。尽管EMIB-T与CoWoS-L直接竞争，但CoWoS-L在技术成熟度和良率方面的优势预计将使其在2028年之前继续保持AI芯片主流封装技术的地位。对于英特尔而言，EMIB-T除了扩大封装面积，还让局部硅桥同时承担高速信号和垂直供电，为更大规模的AI芯片集成提供新的封装路径。
从CoWoS-L到EMIB-T，先进封装还要如何往前走
把CoWoS-L和EMIB-T放在一起看，会发现它们竞争的本质已经超出封装技术本身。AI芯片走到今天，已经很难只靠把晶体管做小来换取性能增长，越来越多的计算Die、Chiplet和HBM被集成进同一个封装，封装本身也开始成为芯片设计的一部分。CoWoS-L选择继续扩大中介层，并通过RDL和局部硅互连完成不同区域的连接。EMIB-T则沿着嵌入式硅桥继续推进。路线不同，但目标很接近，都是想让更多计算资源和存储资源在一个封装里高速协同。TrendForce也因此判断，未来几年AI芯片的先进封装竞争仍会围绕更大尺寸和更高互连密度展开。
但封装越做越大，2.5D封装自身也开始遇到越来越多的困难。
先看互连。AI芯片内部的数据交换量已经大到一个程度，单纯增加计算单元并不够，算出来的数据还得尽快送达下一颗Die和HBM。距离、线宽、布线数量都会影响传输速度，也会影响功耗。于是，封装里如何布局、哪些芯片应该放得更近，已经开始影响芯片性能。以前可以把封装理解成芯片制造完成之后的最后一步，现在这个说法不够准确。对于Chiplet架构来说，Die如何排布、互连怎么实现等，是需要一起考虑的。业内也越来越重视package-level co-design，即在芯片设计、封装和系统设计阶段就同时考虑电、热、机械等问题。
散热和良率同样是2.5D封装继续之后绕不开的问题。现在的AI加速器已经是高功耗器件，封装里放的芯片越多，局部热量也越集中。2.5D至少还能把GPU、ASIC和HBM横向铺开，给散热留下空间，但横向空间终究有限。
良率方面，一颗AI芯片的价值本来就不低，现在一个封装里又集成了多颗计算Die、HBM和大量互连结构，任何一个环节出问题，都可能影响整个封装。芯片数量增加以后，制造、键合、测试和失效分析都需要更加精细。尤其到了超大尺寸封装阶段，大家看的已经不只是能不能做出来，还要看能不能稳定地做出来，而且要把成本压下来。
既然2.5D封装有这些困境，为什么不干脆放弃它，全面转向3D封装？从技术能力来看，3D封装当然能够进一步提高单位面积的集成密度。台积电SoIC已经支持逻辑芯片与逻辑芯片、存储与逻辑芯片之间的3D集成，3nm SoIC堆叠技术也已经在2025年进入量产。但对于高功耗AI逻辑芯片来说，大规模3D封装仍然面临散热、供电和良率三方面挑战。热量会被困在堆叠结构内部，供电需要穿过更多层，任何一层出问题都可能拖垮整个封装。更关键的是，3D封装在技术和成本上都不够成熟，其需要多次流片和多套掩模版，开发和生产成本远高于传统SoC，制造工艺复杂且良率较低，进一步推高了单位成本。同时，台积电CoWoS技术已实现十年量产，良率稳定在90%以上，而3D封装的良率提升仍依赖键合精度改进。目前只有少数技术领先的企业具备开发3D封装的能力，且主要应用于对价格不敏感的高端市场。因此，2.5D封装仍更适合作为现阶段大规模AI芯片集成的主流路径。
所以，先进封装的下一场竞争，不会只追求封装尺寸。尺寸当然还会继续增长，互连密度也还会继续提高，但与此同时，信号完整性、电源完整性、散热、良率和成本都会成为必须一起解决的问题。芯片厂商也不能等到芯片设计完成之后再决定采用哪种封装，封装能力很可能从设计最开始就参与进来。再往后看，HBM的发展也会继续给封装施压。HBM容量和带宽持续提升，意味着单个AI封装需要承载的存储资源越来越多。计算Die继续增加，也会让芯片之间的数据交换更加频繁。封装、HBM和计算芯片之间的关系会越来越紧密，甚至可能出现为了封装去改芯片的情况。
结语
CoWoS-L和EMIB-T其实只是这一轮变化中的两个节点。它们解决的是今天AI芯片规模迅速膨胀之后最现实的问题。下一步真正考验产业链的，是能不能把更多芯片放在一起之后，依然让它们跑得快、散得掉热、及时供电，而且还能稳定量产。AI芯片还在继续变“大”，封装也只能跟着往前走。
下一轮边界会出现在哪里，值得我们持续关注。
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The semiconductor industry
With the continued development of the AI chip, advanced sealing has become an old concept. TrendForce's recent publish report provides a judgement on the advanced encapsulation competition patterns of the AI chip. The report states that, although programmes such as Intel Emib-T are seeking AI chip clients, CoWos-L, with its technological maturity and probabilities, is expected to remain an advanced and mainstream cover programme for AI chips by 2028. This judgement means that the competition for the encapsulation route of the AI chip in the coming years will revolve around CoWoS-L, and that other options will need to be more convincing in maturity and probabilities if they are to enter the market.
Why is the cover of the AI chip getting bigger?
The AI chip is getting bigger and bigger. But here's the big one, which points first to the seal, not to the single calculated chip itself. As the size of the LLM parameters and the complexity of the reasoning missions continues to increase, the AI accelerator requires higher calculus and greater memory bandwidth. Since it is difficult for a single chip to cover all needs on its own, Chiplet and HBM have become important tools for enhancing systemic performance. There is an increasing number of computing and storage resources that need to be connected within the chip, and the pressure is transmitted directly to the envelope.
A good example is the British-Vedda Rubin platform. According to publicly available information, Rubin GPU uses 336 billion transistor tubes equipped with HBM4, with a single GPU of up to 288GBVRAM and 22TB/s memory bandwidth. AMD is also accelerating the trajectories, with the Instinct MI400 series using the Chiplet structure, and the next generation MI455X consists of eight computing chips for the 72 GPU Helios Array System. A common denominator of these products is the increase in the number of computing chips and HBMs integrated into individual packagings. In terms of size, the Blackwell GPU has reached approximately 3.3 times the mask limit in British Weidar and the next generation of Rubin platforms is expected to reach four times.
As the numbers of chips and HBMs are increasing, it is increasingly difficult for traditional single chips to be stored externally to meet the requirements of AI for bandwidth and data transfer efficiency. More computing chips and HBMs are placed in the same advanced envelope, reducing data transmission distance between chips and providing greater bandwidth through high-density interconnections. Thus, the bulk of the AI chip is reflected in the expansion of the encapsulation. What really continues to increase is the total size of an advanced encapsulation, which requires integration of the computing chip, Chiplet, HBM and high-speed interconnection, rather than the horizontal area of a single logical Die.
In terms of data, the expansion of the containment has been going on for almost a decade. According to the Advanced Encapsulation Technology Trends Report by IDTechExpublish, the CoWoS Silicon-Silient layer size of the build-up from about 1.5 times the mask size in 2016, about 1287 mm2, evolved to the current 3.3 times, about 2831 mm2, and is planned to expand to 5.5 times, about 4719 mm2, by 2026. The expansion of the encapsulation is also directly reflected at the end of the equipment, with 75 mm x 75 mm supported by the newly introduced FC Bonder 75 of HANMI Semiconductor, while the traditional generic encapsulation size is only 20 mm x 20 mm.
The power of the seal is also expanding from GPU to AI ASIC. TrendForce data show that NVIDIA ' s high-end GPU delivery is expected to increase by about 30 per cent per year in 2026, and AMD pushed MI400 and MI450 in the second half of 2026. In terms of CSP self-study of ASIC, in 2026 deliveries and kinetic energy were most robust in Google, with TPU v7. AWS has been gradually advancing Trainium v3, starting in the second half of the year, and Microsoft and Meta are still dominated by GPU Server, with a smaller amount of ASIC planning. Different types of AI chips are moving towards a higher degree of integration, which means that the encapsulation requires a continuous increase in computing and storage resources.
Why are there bottlenecks in containment?
When the size of the encapsulation expands, the problem follows. Is there any way to make a middleman of this size?
In the traditional 2D envelope, the chip is connected by a key wiring to the containment panel, where the metal wiring and perforation within the base plate are responsible for signal transmission. The path is long, with greater resistance and perception introduced, and both signal delays and power consumption become bottlenecks. When multiple chips are separated and placed on the PCB, the physical distance of the signal between them is considerable and, in order to drive the signal across this distance, the amount of effort will increase significantly, thus limiting the overall communication bandwidth between the chips.
The size is another problem. The placement of multiple large packagings on PCB would take up large physical areas and would be difficult to accept for space-limited products. More crucially, there is a large gap between the width of PCB ' s wiring and the amplitudes and microcrumbs of the chip, which limits the number and density of I/Os and makes it difficult to meet the requirements of AI and high performance calculations for high bandwidth, low delay and miniaturization. The interconnective length, physical area and I/O density are simultaneously limited, and it is already difficult for 2D seals to continue to carry the integrated demand for AI chips.
To address these problems, some manufacturers have proposed a 2.5-D containment programme. The core idea was to introduce a layer of intermediaries, with multiple chips and emissions placed on them, rather than directly on PCB. The chip is connected to the intermediate layer through a microcrumb, which contains an extremely fine heavy distribution layer, responsible for high-density, short-range horizontal communication between the chips. The intermediate layer is then connected vertically through a silicon cone to the lower encapsulation panel. As a result, the interconnectivity of the chips has been significantly reduced, the signal integrity and bandwidth have been improved, while the impenetrable mask limits of a single chip have been bypassed, and a viable path for subsequent integration of more computing chips and HBMs has been provided.
It is also on the 2.5D-enabled path that CoWos, which accumulates electricity, is becoming a representative option.
COWOS-L: 2.5D mainstream programme
CoWoS, a typical 2.5D containment programme, is based on the integration of multiple SOCs or Chiplet and HBMs in one cover.
The current CoWos family consists mainly of three members: CoWos-S, CoWos-R and CoWos-L. The most important difference is that there are different ways of achieving it at the intermediary level. CoWoS-S uses a wide silica-based intermediate layer, where high density interconnection is achieved by wiring, bringing together the logical chips and HBM. COWOS-R replaces Silicon Intermediaries with RDL. The RDL consists of polymers and copper wiring layers, which are better mechanically flexible while maintaining high interconnectivity, and can be more easily extended to support larger containment dimensions.
COWOS-L is a more flexible way of integrating on the basis of the former. It is wired on the basis of RDL and is embedded in a small silica called local silica interconnection. The L letter of CoWoS-L corresponds to the Local Silicon Interconnection (LSI), i.e. local silicon interconnection. Accumulation indicates that LSI interconnects di-to-die to achieve high wiring density through multilayered sub-maritic copper lines, with so-to-SoC, SoC-to-Chiplet and SOC-to-HBM being covered by different product needs. At the same time, RDL is responsible for the wider transmission of signals and power. In this way, high-density interconnections are concentrated in areas where there is a real need for precision connectivity, rather than having the same high-density wiring carried by the entire middle layer.
This structural change is key to the ability of CoWoS-L to continue to expand the containment. For ultra-large AI chips, not every area in the envelope requires an equally high wiring density. If all regions use high-density wiring in silicon-mediated layers, manufacturing costs and process complexity will increase simultaneously as the area expands. COWS-L, through a combination of LSI and RDL, uses high-density interconnections where they are really needed, and uses RDL to provide greater connectivity and power, thus allowing for further expansion of the entire encapsulation while maintaining the interconnectivity of critical areas. It has now positioned CoWos-L in support of the larger HPC product containment programme and has continuously expanded its intermediate layer to incorporate more silicon chips and HBMs.
This idea of local high density plus large area expansion also provides a better match between CoWos-L and the Chiplet structure of the AI chip. The future AI accelerator may consist of multiple calculations of Die, different functions of Chiplet and multiple HBMs, while data streams between different chips are not identical. Some links require very high bandwidth and very short connectivity distances, while others focus more on the distribution of signals and power sources between regions. CoWoS-L can either configure interconnectivity structures for these different needs or further integrate independent embedded deep-drum tanks eDTCs below SOC to improve power management. In other words, the seals began to move from a simple connection chip to an interconnective and power-driven design for the entire computing system.
From the actual size, CoWos-L has also been removed from the laboratory. CoWoS-L, a 3.5-fold retial size of the yield, had entered production in 2024. According to information released in 2025, the company has completed the 5.5-fold mask/reticle-sized CoWos programme and plans to start production in 2026 to meet AI and HPC ' s need for higher performance. It also indicated that the CoWos intermediate layer would continue to be expanded to accommodate more advanced process chips and HBMs.
This technical route has also begun to land the product. TrendForce states that the NVIDIA and AMD ' s AI accelerators have already used CoWos-L and MTIA 400 in Meta have also used this package. As cloud service providers continue to develop their own ASIC, more SoC, Chiplet and HBM will need to be integrated in the same envelope, and Microsoft and AWS are expected to import CoWoS-L in 2027. TrendForce believes that CoWoS-L, with its technological maturity and probabilities, is expected to maintain the mainstream advanced encapsulation programme of AI chips by 2028.
However, CoWos-L is not the only path of realization for the 2.5D envelope.
EMIB, where's the other technical route?
If CoWos-L was written on the intermediary level, the EMIB in Intel followed another 2.5-D containment route. EMIB is known as Embedded Multi-die Interconnect Bridge, an embedded multi-chip bridge. Instead of using a large silica intermediate layer covering the entire area of the envelope, it embeds smaller silica bridges into the encapsulation base, only to establish a connection between the chips that require a high density interconnection. The chips remain on the base plate in parallel, but can be transmitted at high density and high speed through a silicon bridge between them.
EMIB's thinking is more local than that of a large silica-mediated layer. Silicon bridges are located only in areas where chips require high-speed communications, and therefore there is no need for a complete silicon intermediate layer for the entire envelope. Intel describes how EMIB can customize the size and type of the bridge for different di-to-die connections, establishing a high-density interconnection between the logical chip and the logical chip, the logical chip and HBM, while avoiding allowing all signals and power to pass through a whole silica layer. This would increase the interconnectivity between the different chips and allow a trade-off between containment structures and costs.
This structure is particularly appropriate for the Chiplet structure. A package can be placed in multiple cores from different process nodes, different functions, which can then be connected through the EMIB bridge at different locations, so that different types of chips such as CPU, GPU, I/O and HBM can form a complete system. Intel has already used EMIB for large-scale production and has indicated that its encapsulation assembly performance can be close to that of the traditional FCBGA seals, which are of comparable complexity.
However, EMIB has its own limitations. Since the Silicon Bridge is embedded in the encapsulation base, rather than covering the full encapsulation of the large silicon intermediate layer, the high-density connection between the chips is ultimately still affected by the base plate wiring capacity. With the increasing bandwidth of HBM, data transmission within the AI chip is increasing, and power supply is beginning to become an important issue in addition to interconnectivity density. For high-capacity AI chips, the rapid and steady transfer of sufficiently large currents to the chip in a limited containment space, while reducing power noise and transmission losses, has become key to EMIB ' s further development.
EMIB-T is the promotion programme that has emerged in this context. T corresponds to Through-Silicon Via, which is a silicon cone. Intel adds TSV to the original EMIB local silicon bridge, which allows power to be delivered directly from the containment base plate vertically to the upper chip, without having to bypass other wiring layers. This will reduce the power supply path, increase the intensity of the power supply and improve the integrity of the power supply in high power consumption and high bandwidth applications. Intel public information suggests that EMIB-T can also integrate multiple layers of copper power within the bridge, the terrestrial network and high-density electrical capacity, thus further reducing resistance and noise in the power network.
If EMIB is seen as a bridge to the chip, the biggest change for EMIB-T is to add a vertical channel to the bridge. In the past, the main solution was how the chips were communicated between them and, with the inclusion of TSV, the sealing could further address the question of how electricity could be delivered directly. The EMIB-T programme, presented by Intel on ECTC in 2026, has reduced the first layer of condensation to 25 micrometres, expanded the containment dimension to 120 mm x 120 mm and supported the integration of more than nine reticle areas with storage chips, with high-speed connections to 12 Gb/s HBM4e and 64 Gb/s UCIe.
This means that EMIB is moving further from the original local silicon bridge to a larger size, higher interconnectivity density and greater power supply capacity. According to TrendForce, with the continued attention paid to the costs of CoWos-L sealing and advanced telecommunications capacity, EMIB became an alternative for some AI chip manufacturers, and Google expects to adopt EMIB-T in 2027, and AWS is testing EMIB technology. Despite direct competition between EMIB-T and CoWos-L, CoWos-L ' s advantages in terms of technological maturity and probabilities are expected to maintain its position as a mainstream cover technology for AI chips by 2028. For Intel, the EMIB-T, in addition to expanding the area of encapsulation, provides a new encapsulation route for larger AI chip integration by providing local silicon bridges with high-speed signal and vertical power.
From CoWoS-L to EMIB-T, how to move forward with the advanced seal
The combination of CoWos-L and EMIB-T reveals that their competition is by its very nature beyond the containment technology itself. The AI chip has come to this point with little transistor in exchange for performance growth, and more and more Die, Chiplet and HBM are being integrated into the same envelope, which itself is beginning to become part of the chip design. COWOS-L chooses to continue to expand the intermediate layer and to connect the different regions through RDL and local silicon interconnections. EMIB-T continues to advance along the embedded Silicon Bridge. The route is different, but the goal is very close, with the intention of allowing more computing and storage resources to work together in one envelope at high speed. TrendForce thus concluded that the advanced containment competition for AI chips would continue to revolve around larger sizes and higher interconnectivity density in the coming years.
However, the larger the cover, the more the 2.5D cover itself began to encounter increasing difficulties.
Look at the interconnection. The amount of data exchanged within the AI chip has reached a level where simply adding computing units is not sufficient, and the resulting data must reach the next Die and HBM as soon as possible. Distance, width and number of wires affect transmission speed and power consumption. As a result, the layout of the envelope and which chips should be put closer together have begun to affect the chip performance. It had previously been possible to interpret the seal as the last step after the chip had been manufactured, and that statement was now not accurate. In the case of the Chiplet structure, the way in which Dié is bilged and interconnected needs to be considered together. There is also a growing focus within industry on package-level co-design, i.e., consideration of electrical, heat, mechanical, etc. at the chip design, containment and system design stages.
Dispersion and benign rates are also issues that cannot be bypassed after 2.5D seals continue. The current AI accelerator is already a high-powered device, and the more chips are placed in the encapsulation, the more the local heat is concentrated. At a minimum, 2.5D provides horizontal spread of GPU, ASIC and HBM, leaving room for heat dispersion, but later there is limited horizontal space.
In terms of probabilities, the value of an AI chip is not insignificant, and now it's a cover that has multiple calculations of Die, HBM and a large number of interconnective structures, and any link that has a problem could affect the entire envelope. With the increase in the number of chips, the manufacture, binding, testing and failure analysis need to be more sophisticated. In particular, when it comes to oversized seals, you see not only whether it can be done, but whether it can be done in a stable manner, but also at a cost.
Given these dilemmas of 2.5D, why not simply abandon it and turn to 3D? In terms of technological capability, 3D sealing can certainly further increase the integrated density of the unit area. The build-up SOIC has supported the 3D integration between the logical chips and the logical chips, the storage and the logical chips, and the 3nm SoIC stacking technology has been in production since 2025. However, for high-capacity AI logical chips, large-scale 3D seals still face the challenges of dissipation, electricity and good rates. The heat will be trapped inside the stacking structure, the power will need to pass through more layers, and any layer may be able to bring down the entire seal. More crucial is the fact that the 3D seals are not technically and costly mature and require multiple streaming and masking, that the development and production costs are much higher than the traditional SOC, and that the manufacturing process is complex and less benign, further pushing unit costs. At the same time, the COWOS technology has achieved 10 years of production and has stabilized at over 90 per cent, while 3D-enhancement improvements are still dependent on improvements in key accuracy. Only a few of the technology-leading enterprises currently have the capacity to develop 3D seals, which are mainly applied to high-end markets that are not price-sensitive. As a result, 2.5D envelopes are still better suited as the mainstream path for the current phase of large-scale AI chip integration.
So, the next competition for advanced seals, not just the size of the seals. Sizes will certainly continue to grow and interconnectivity will continue to increase, but at the same time signal integrity, power integrity, heat dispersion, good rates and costs will all need to be addressed together. Nor can the chip manufacturer wait until the chip design has been completed to decide which seal to use, which capacity is likely to be involved from the very beginning of the design. In the future, HBM development will continue to pressure the seal. The constant increase in HBM capacity and bandwidth means that individual AI envelopes require more and more storage resources. The continued increase in the calculation of Die will also increase the frequency of data exchange between chips. The relationship between the envelope, HBM and the calculated chip is becoming ever closer and there may even be cases where the chip is modified for the cover.
Concluding remarks
CoWOS-L and EMIB-T are in fact just two nodes of the change in this round. They solve the most real problem of today's rapid expansion of the size of the AI chip. The real test of next step is whether more chips can be put together to keep them running fast, dissipated, powered in a timely manner and able to stabilize production. The AI chip continues to be “big” and the seal can only follow.
Where the next round of borders will be, it deserves our continued attention.
Auto-fetched and translated by AI Gem Box. All rights belong to the original author.